1. Field of the Invention
The present invention relates to a structure and a method of fabricating a DRAM cell, or more in particular to a method of fabricating a memory cell of capacitor on bit-line type (COB) in which at least a bit line is formed first, and then at least a memory capacitor is formed on the bit line.
2. Description of the Related Art
The integration scale of semiconductor memory devices, especially, that of the dynamic RAM is ever on the increase every year. The resulting tendency is toward a further reduced area occupied by a unit memory element. A three-dimensional cell structure is therefore essential for securing a memory cell capacity sufficient for read and write operations (more than 20 fF). This has promoted general applications of cell structures using a trench-type capacitor and a stack-type capacitor.
A conventional method of fabricating a stack-type capacitor concerns a COB (capacitor over bit-line) memory cell as disclosed in, for example, xe2x80x9cA CAPACITOR-OVER-BIT-LINE (COB) CELL WITH A HEMISPHERICAL-GRAIN STORAGE NODE FOR 64 Mb DRAMs,xe2x80x9d by M. Sakao et al., IEDM Technical Digest, pp. 655, 658, 1990.
This device will be described in detail below with reference to drawings.
FIG. 27 is a plan view showing a COB memory cell, FIG. 28 a perspective view taken diagonally from above the memory cell of FIG. 27, FIGS. 29, 30, 32 sectional views taken in line XXIXxe2x80x94XXIX in FIG. 27, showing semiconductor structures in the fabrication steps of the COB memory cell, and FIG. 31 a sectional view taken in line XXXIxe2x80x94XXXI in FIG. 27, showing a semiconductor structure in the fabrication step of the COB memory cell.
As shown in FIG. 29, first, an element-isolating oxide film 13 is formed on a silicon substrate 11 using the LOCOS process, while at the same time forming at least an element region 14. Next, a gate oxide film (not shown) is formed. Polysilicon gate electrodes 19 each having the upper surface and the sidewalls thereof covered with a silicon oxide film are formed on the gate oxide film. Contact holes are opened to the gate electrodes 19 in self-alignment on the element region 14, and a polysilicon film is deposited to form interconnects 50 (FIG. 29).
As shown in FIG. 30, a first interlayer insulating film 51 is deposited over the whole surface. The first interlayer insulating film 51 is patterned using a bit line contact pattern 52 thereby to form a bit line contact hole 53. Polysilicon 54 with impurities introduced therein is filled in the bit line contact hole 53. Then, a bit line 55 is formed using a tungsten polycide (FIG. 30).
As shown in FIG. 31, a second interlayer insulating film 56 is deposited over the whole surface of the bit line 55 and flattened. At least a storage node contact hole 57 is opened, thereby forming HSG (hemispherical grain) storage nodes 58 connecting to the interconnects 50 (FIG. 31).
As shown in FIG. 32, a capacitor insulating film (not shown) made of a silicon oxide thin film and a silicon nitride thin film is formed over the whole surface, followed by forming plate electrodes 59 by depositing polysilicon. Then, a third interlayer insulating film 60 is deposited on the whole surface thereby to form metal wires 61 (FIG. 32).
The DRAM memory cell fabricated using the prior art has the following problems:
(1) The interconnects 50 are inserted under the bit line 55, so that the height of the bit line contact 52 is increased, resulting in an increased aspect ratio.
(2) The bit line contact 52 extends from the bit line to a diffusion layer, and therefore the aspect ratio of the bit line contact increases.
(3) The interconnects 50 are formed in the vicinity of the bit line contact 62 of an adjacent element region. Therefore, the interconnects 50 are liable to short with the polysilicon 54 in the bit line contact by misregistration.
(4) Since the bit line contact 52 is not formed in self-alignment with respect to the gate electrodes 19, a short is liable to occur between the bit line and the gate electrodes.
(5) A new lithography process is required for forming the interconnects 50, leading to an increased number of fabrication steps.
In view of the above-mentioned problems of the prior art, it is an object of the present invention to provide a memory cell structure and a method of fabricating a memory cell, in which the aspect ratio of the capacitor contact and the bit line contact can be reduced in forming a COB DRAM cell, misregistration has a lesser effect and the number of fabrication steps is not unduly increased.
According to the present invention, there is provided a semiconductor memory device comprising: a semiconductor substrate; an element-isolating oxide film formed on the semiconductor substrate for defining an element region; a first interlayer insulating film formed on the element region and the element-isolating oxide film; a first contact hole formed in the first interlayer insulating film and extending over the element region and the element-isolating oxide film, the first contact hole reaching the semiconductor substrate; and a first conductive film connected to the element region for filling the first contact hole. The semiconductor memory device may further comprise: a second interlayer insulating film formed on the first interlayer insulating film and the first conductive film; a second contact hole formed in the second interlayer insulating film and reaching the first conductive film above the element-isolating oxide film; and a wiring layer connected to the first conductive film through the second contact hole.
The semiconductor memory device may further comprise: a third contact hole formed in the first interlayer insulating film and reaching the semiconductor substrate at the element region; and a second semiconductive film filling the third contact hole.
The semiconductor memory device may further comprise a gate insulating film formed on the element region between the first contact hole and the third contact hole and a gate electrode extending over the gate insulating film.
The semiconductor memory device may further comprise: a third interlayer insulating film formed on the second interlayer insulating film and the wiring layer; a fourth contact hole formed through the third interlayer insulating film and the second interlayer insulating film and reaching the second conductive film; and a first electrode formed on the third interlayer insulating film and connected with the second conductive film through the fourth contact hole.
The semiconductor memory device may further comprise: a capacitor insulating film formed on the first electrode; and a second electrode formed on the capacitor insulating film.
According to the present invention, there is further provided a semiconductor memory device comprising: a semiconductor substrate; an element-isolating oxide film formed on the semiconductor substrate for defining an element region; a data transfer MOSFET formed on the element region and having a gate electrode thereof connected to a word line; a first interlayer insulating film covering the element-isolating oxide film and the MOSFET; a first contact hole formed in the first interlayer insulating film and extending over the element region and the element-isolating oxide film, the first contact hole reaching one of the source/drain diffusion layers of the MOSFET; a second contact hole formed in the first interlayer insulating film and reaching the other of the source/drain diffusion layers of the MOSFET on the element region; a first conductive plug filling the first contact hole; a second conductive plug filling the second contact hole; a second interlayer insulating film covering the first interlayer insulating film, the first conductive plug and the second conductive plug; a bit line contact hole formed in the second interlayer insulating film and reaching the first conductive plug above the element-isolating oxide film; a third conductive plug filling the bit line contact hole; a bit line formed on the second interlayer insulating film and the third conductive plug; a third interlayer insulating film formed on the second interlayer insulating film and the bit line; a storage node contact formed through the third interlayer insulating film and the second interlayer insulating film, and reaching the second conductive plug; and a storage node electrode, a capacitor insulating film and a plate electrode sequentially formed on the third interlayer insulating film and the storage node contact.
According to the present invention, there is still further provided a method of fabricating a semiconductor memory device, comprising the steps of: forming an element-isolating oxide film for defining an element region on a semiconductor substrate; forming a first interlayer insulating film on the element region and the element-isolating oxide film; forming a first contact hole in the first interlayer insulating film, the first contact hole extending over the element region and the element-isolating oxide film and reaching the semiconductor substrate; and filling the first conductive film in the first contact hole.
The method of fabricating a semiconductor memory device may further comprise the steps of: forming a second interlayer insulating film on the first interlayer insulating film and the first conductive film; forming a second contact hole in the second interlayer insulating film, the second contact hole reaching the first conductive film above the element-isolating oxide film; and forming a wiring layer on the second interlayer insulating film, the wiring layer being connected to the first conductive film through the second contact hole.
The method of fabricating a semiconductor memory device may further comprise the steps of: forming a third contact hole in the first interlayer insulating film at the same time of forming the first contact hole, the third contact hole reaching the semiconductor substrate on the element region; and filling the second conductive film in the third contact hole at the same time of filling the first conductive film in the first contact hole.
The method of fabricating a semiconductor memory device may further comprise the steps of: forming a gate-insulating film on the element region between the first contact hole and the third contact hole; and forming a gate electrode extending on the gate-insulating film and the element-isolating oxide film; wherein the first contact hole and the third contact hole are formed in self-alignment with respect to the gate electrode.
The method of fabricating a semiconductor memory device may further comprise the steps of: forming a third interlayer insulating film on the second interlayer insulating film and the wiring layer; forming a third contact hole in self-alignment with respect to the wiring layer, the third contact hole reaching the second conductive film through the third interlayer insulating film and the second interlayer insulating film; and forming a first electrode connected to second conductive film through the third contact hole on the third interlayer insulating film.
The method of fabricating a semiconductor memory device may further comprise the steps of: forming a capacitor insulating film on the first electrode; and forming a second electrode on the capacitor insulating film.
According to the present invention, there is yet further provided a method of fabricating a semiconductor memory device, comprising the steps of: forming an element-isolating oxide film on a semiconductor substrate; forming a data transfer MOSFET having a gate electrode connected to a word line on an element region defined by the element-isolating oxide film; forming a first interlayer insulating film on the MOSFET and the element-isolating oxide film; forming a first contact hole and a second contact hole simultaneously in the first interlayer insulating film, the first contact hole extending on the element region and the element-isolating oxide film and reaching one of the source/drain diffusion layers of the MOSFET, the second contact hole reaching the other of the source/drain diffusion layers of the MOSFET on the element region; forming a first conductive plug filling the first contact hole; forming a second conductive plug filling the second contact hole; forming a second interlayer insulating film on the first interlayer insulating film, the first conductive plug and the second conductive plug; forming a bit line contact hole in the second interlayer insulating film, the bit line contact hole reaching the first conductive plug above the element-isolating oxide film; forming a third conductive plug filling the bit line contact hole; forming a bit line on the second interlayer insulating film and the third conductive plug; forming a third interlayer insulating film on the second interlayer insulating film and the bit line; forming a storage node contact hole reaching the second conductive plug through the third interlayer insulating film and the second interlayer insulating film; and forming a storage node contact having a storage node electrode, a capacitor insulating film and a plate electrode sequentially on the third interlayer insulating film and the storage node contact hole, thereby forming a capacitor.
In the method of fabricating a semiconductor memory device, the step of forming the first conductive plug and the second conductive plug may include the substeps of depositing a conductive film over the whole surface of the semiconductor substrate and etching the conductive film by a chemical mechanical polishing process.
The method of fabricating a semiconductor memory device may further comprise the step of forming an insulating film on the upper surface and the sidewalls of the gate electrode, the insulating film acting as a stopper against the chemical mechanical polishing process when the conductive film is etched by the chemical mechanical polishing process.
According to the present invention, there is further provided a semiconductor memory device comprising: a semiconductor substrate; an element-isolating insulating film formed on the surface of the semiconductor substrate for defining an element region; a MOS transistor formed in the element region; a first interlayer insulating film formed on the MOS transistor; a first plug formed over one of the source and drain regions of the MOS transistor and the element-isolating insulating film, the first plug being opened to the first interlayer insulating film; a second plug formed by the same layer as the first plug over the other of the source and drain regions of the MOS transistor, the second plug being opened to the first interlayer insulating film; a bit line formed on the first interlayer insulating film and connected to the first plug; a second interlayer insulating film formed on the bit line and the first interlayer insulating film; and a capacitive element formed on the second interlayer insulating film and connected to the second plug through the opening formed in the second interlayer insulating film.
In the semiconductor memory device, the semiconductor substrate and the first conductive plug may be in contact with each other by way of a surface and the sides of the semiconductor substrate.
In the semiconductor memory device, the third conductive plug and the first conductive plug may be in contact with each other by way of the upper surface and the sides of the first conductive plug.
In the semiconductor memory device, the length of the first conductive plug along the gate electrode is substantially the same as the length of the element region along the gate electrode.
In the semiconductor memory device, the first conductive plug extends to a position deeper than the surface of the semiconductor substrate on an element-isolating region only in the vicinity of the boundary between the element-isolating region and the element region.
The use of this invention with a COB DRAM cell permits a self-aligned polysilicon plug to be formed on the source and drain. A bit line contact and a storage electrode contact are formed on this polysilicon plug thereby to reduce the aspect ratio of both the bit line contact and the storage electrode contact.
Further, a polysilicon plug according to this invention is formed in self-alignment with respect to a gate electrode. The shorting with a contact on an adjacent element region or between the plugs of the source and drain never occur. This polysilicon plug, therefore, is considered highly protective against misregistration.
Furthermore, an independent lithography process is not required for forming a polysilicon plug according to the invention, and therefore the number of fabrication steps is reduced.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.